Bump Adhesion/Electrical Connectivity
Early detection and correction of problems related to bump adhesion/electrical connectivity
is especially important for manufacturers because completed wafers
make very expensive scrap.
The fact that the testing of the individual dies does not take
place until the dies have been packaged, increases significantly
IC production cost.
This increased cost stems from the greater complexity,
size, and quantity of the testing apparatus, as well as from the difficulty
of manipulating large quantities of separately packaged dies.
Bump adhesion/ electrical connectivity inspection can contribute dramatically to process profitability.
There are several methods for testing bump integrity.
Most foundries are using optical tools to look for missing bumps
and to measure bump height.
Scanning Electronic Microscope (SEM) is used to check bump shape
and solder-UBM interface.
X-ray tools are used to discover voids and Shear Strength tools
are used to check strength of bump adhesion.
However, all methods described above have a common disadvantage, i.e.,
they are based on information collected by mainly optical means such
as bump height and co-planarity, as well as defects such as misplaced
bump, misshaped bump, bridged bump, shear bump, extra satellite,
missing metal, CDs, excess resist, particles, cracks, scumming,
chemical residue, etc. End-users attempt to extrapolate whether
there are electrical connection between the die and a package or circuit
board from indirect observations.
As of today only RST method allows manufacturers to test connectivity
or integrity of bumps formed on a semiconductor wafer/die by directly
measuring contact conditions on the interface between the bump and
the wafer/die. Furthermore, it provide end-user with
information of whether problem with bump adhesion/electrical connectivity
or quality of adhesion/electrical connectivity
on each individual bump exists and provide evaluation of the electrical
integrity of the die.
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